The surface configuration of an integrated circuit device, particularly one employing silicon as the bulk material of the substrate wherein device regions are formed, will vary depending upon the type of surface passivation processing employed. For example, recess or trench-processed substrates and LOCOS (Local oxidation of silicon) -formed structures have an undulating surface configuration, while devices formed using direct moat processing techniques are effectively planar-surfaced. Because of the variations in thickness of field insulator material or change in surface shape of the bulk of an integrated circuit device manufactured using the former two techniques, integration density and immunity to external influences (e.g. radiation hardness) of the resulting structures are reduced compared with a planar-surfaced structurre formed by direct moat (e.g. via a field oxide) processing. For a discussion of the above-referenced techniques and their effects on integrated circuit manufacture, attention may be directed to an article by K.L. Wang et al entitled "Direct Moat Isolation for VLSI", published by the IEEE in IEDM 81, pages 372-375.
As described in the Wang et al article, direct moat wafer processing has recently been recognized as offering a number of advantages over previous methodologies for processing large scale integrated circuits. In the manufacture of circuits containing field effect devices, the field oxide that is formed on the planar surface of the substrate and used to prevent the creation of unwanted parasitic devices beneath overlying interconnect material (e.g. metal, polysilicon), has formed therein apertures or windows through which dopants for forming device regions are introduced, and within which gate electrodes (e.g. polysilicon) are provided.
An illustration of an exemplary embodiment of an apertured field oxide layer for forming a field effect device in a semiconductor (e.g. silicon) substrate using direct moat processing is shown in FIGS. 1-8, of which FIGS. 1, 3, 5 are plan views of the device, while FIGS. 2, 4, 6 are sectional views taken along line A--A' of FIGS. 1, 3, 5, respectively. FIG. 7 is a sectional view taken along line B--B' of FIG. 3, while FIG. 8 is a sectional view taken along C--C' of FIG. 3. As shown in FIGS. 1 and 2, a (silicon) substrate 10 having a planar surface 11 has a field oxide layer 12 formed thereon (typically to a thickness on a order of 5000-6000.ANG.). Field oxide layer 12 has an aperture or window 13 formed therein exposing a surface region 14 of the planar surface 11 of substrate 10. The sidewalls 15 of window 13 are effectively perpendicular to planar surface 11, so as to allow subsequent formation of an insulative spacer thereat.
Next, as illustrated in FIGS. 3 and 4, following the formation of a thin dielectric (gate oxide) layer 21 (having a thickness on the order of 100-400.ANG.), gate electrode material (e.g. polysilicon) 25 is nonselectively formed on the top surface 16 of the field oxide layer 12 and on the gate oxide layer 21 within the entirety of the aperture 13. The layer 25 of polysilicon gate material is selectively etched to form a gate electrode 26 which, as shown in FIGS. 5 and 6, overlies the top surface 16 of field oxide layer 12 and extends onto thin gate oxide layer 21. During this step, that portion of the polysilicon layer 25 whereat the gate electrode 26 is to be formed is masked and the exposed polysilicon layer in a direction normal to the surface 11 of substrate 10 down to the surface of field oxide 12 and substrate surface 11, partly removing exposed surface portions of the thin gate oxide layer 21 adjacent to the masked polysilicon gate 26 and the field oxide layer 12. Complete removal of the gate oxide 21 results in etching of the substrate 10 and results in device damage. This constraint limits the etch of the polysilicon.
More particularly, the etch of the polysilicon proceeds uneventfully until a thickness t in FIG. 5 is removed. At that point the gate oxide 21 becomes exposed to the etch environment in those regions away from the field xoide edge 15. Once exposed the gate oxide begins to etch. Should all of the gate oxide be etched away, the etch will proceed into the silicon substrate and destroy the device. Stopping the etch before this occurs will, for typical values of gate and field oxides, leave some of the polysilicon having thickness T around the oxide wall. This residual is an unwanted polysilicon stringer 30. Thus the stringer results from two compounding effects. First, the field oxide wall creates wall of polysilicon with thickness T greater than the flat film thickness t. Second, the etch is limited in extent by the penetration of the gate oxide under the thinner polysilicon.
In our copending U.S. patent application entitled "Technique for Elimination of Polysilicon Stringers in Direct Moat Field Oxide Structure", U.S. Ser. No. 841,297, filed Mar. 19, 1986 and assigned to the Assignee of the present application, there is disclosed a scheme for solving the problem of the unwanted residual polysilicon stringer along the sidewall of the aperture in a field oxide layer employed in direct moat wafer processing. Pursuant to that inventive processing technique, the sidewall of the aperture in the field oxide layer is initially sloped prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the taper or slope of the sidewall of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent selective etching of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringer) that could be a source of device contamination. After the polysilicon gate has been delineated, the sloped sidewall of the aperture in the field oxide is removed (by anisotropic etching), so that the sidewall of the aperture or window of the field oxide layer will be perpendicular to the planar surface of the substrate, thereby ensuring the requisite functional continuity throughout substantially the entire portion of the field oxide adjacent the aperture therein.
In the completed structure the only portion of the field oxide that has a reduced thickness is that original tapered portion lying directly beneath the polysilicon gate. While this small region is not necessarily a catastrophic problem in terms of functional continuity of the field oxide layer, it would be preferred that no portion of the field oxide layer have a tapered thickness, so as to effectively completely obviate any potential region of reduced radiation hardness and/or leakage beneath the gate electrode.